AD9644：14位串行模數(shù)轉(zhuǎn)換器概述

AD9644是一款14位雙通道模數(shù)轉(zhuǎn)換器(ADC)，配有一個(gè)高速串行輸出接口，采樣速度可為80MSPS或155MSPS。這款雙通道ADC內(nèi)核采用多級(jí)、差分流水線(xiàn)架構(gòu)，并集成了輸出糾錯(cuò)邏輯。每個(gè)ADC均具有寬帶寬、差分采樣保持模擬輸入放大器，支持用戶(hù)可選的各種輸入范圍。集成基準(zhǔn)電壓源可簡(jiǎn)化設(shè)計(jì)。占空比穩(wěn)定器可用來(lái)補(bǔ)償ADC時(shí)鐘占空比的波動(dòng)，使轉(zhuǎn)換器保持出色的性能。

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS. The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.

Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

特性：

JESD204A coded serial digital outputs

SNR = 73.7 dBFS at 70 MHz and 80 MSPS

SNR = 71.7 dBFS at 70 MHz and 155 MSPS

SFDR = 92 dBc at 70 MHz and 80 MSPS SFDR = 92 dBc at 70 MHz and 155 MSPS

Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS

1.8 V supply operation

Integer 1-to-8 input clock divider

IF sampling frequencies to 250 MHz

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS

Programmable internal ADC voltage reference

Flexible analog input range: 1.4 V p-p to 2.1 V p-p

ADC clock duty cycle stabilizer

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

應(yīng)用：

Communications

Diversity radio systems

Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment.

產(chǎn)品優(yōu)點(diǎn)：

1. An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock.

2. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs.

3. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz.

4. Operation from a single 1.8 V power supply.

5. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

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AD9644：14位串行模數(shù)轉(zhuǎn)換器應(yīng)用詳解（原創(chuàng)）摘要：這 款雙通道ADC內(nèi)核采用多級(jí)、差分流水線(xiàn)架構(gòu)，并集成了輸出糾錯(cuò)邏輯。每個(gè)ADC均具有寬帶寬、差分采樣保持模擬輸入放大器，支持用戶(hù)可選的各種輸入范 圍。集成基準(zhǔn)電壓源可簡(jiǎn)化設(shè)計(jì)。占空比穩(wěn)定器可用來(lái)補(bǔ)償ADC時(shí)鐘占空比的波動(dòng)，使轉(zhuǎn)換器保持出色的性能。本文詳解AD9644內(nèi)部構(gòu)成及應(yīng)用中的注意事項(xiàng)。