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[導(dǎo)讀]對(duì)于keil的啟動(dòng)代碼(針對(duì)STM32F042),添加 備注 和 自己的理解;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************;* File Name : startup_stm32f042.s;* Author : MCD

對(duì)于keil的啟動(dòng)代碼(針對(duì)STM32F042),添加 備注 和 自己的理解

;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f042.s
;* Author : MCD Application Team,modified by Sky,
;* Version : V1.5.0;* Date : 05-December-2014,modified on,01-Nov-2016;* Description : STM32F042 Devices vector table for;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http:;;www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and; limitations under the License.
;
;*******************************************************************************




;
;
;notes:stack,heap,data seg,code seg address of mem is set by compiler
;
;










;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;


;;EQU 定義宏
;;棧大小,1k
Stack_Size EQU 0x00000400;;AREA 定義段,注意:一個(gè)程序是由多個(gè)段構(gòu)成,如CODE,STACK,DATA,
;;ALIGN=3,8字節(jié)對(duì)齊
AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE Stack_Size
;;__initial_sp一個(gè)標(biāo)號(hào),由匯編器進(jìn)行計(jì)算,代表上面SPACE分配內(nèi)存的最后一個(gè)地址,棧為向下增長(zhǎng)型
__initial_sp


; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;

;;堆512bytes
Heap_Size EQU 0x00000200

AREA HEAP, NOINIT, READWRITE, ALIGN=3__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
;;PRESERVE8,指定當(dāng)前文件堆棧8bytes對(duì)齊
PRESERVE8
;;THUMB,后面的指令要兼容THUMB指令
THUMB


; Vector Table Mapped to Address 0 at Reset
;;定義一個(gè)叫做RESET的數(shù)據(jù)段
AREA RESET, DATA, READONLY
;;EXPORT聲明標(biāo)號(hào)為外部文件可用
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
;;DCD是按4字節(jié)分配存儲(chǔ)單元
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler

; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_CRS_IRQHandler ; RCC and CRS
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD TSC_IRQHandler ; TS
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD CEC_CAN_IRQHandler ; CEC and CAN
DCD USB_IRQHandler ; USB

__Vectors_End

__Vectors_Size EQU __Vectors_End - __Vectors

;;定義一個(gè).text的代碼段
AREA |.text|, CODE, READONLY

;STM32F03x devices feature 4Kbytes of static SRAM. STM32F04x devices feature
;6 Kbytes of static SRAM. STM32F05x devices feature 8Kbytes of static SRAM.
;STM32F07xS devices feature 16 Kbytes of static SRAM. STM32F09x devices feature
;32 Kbytes of static SRAM.





; Reset handler routine
;;PROC定義子程序
Reset_Handler PROC
;;WEAK:弱定義
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit


;;給R0賦值,sp的值
LDR R0, =__initial_sp ; set stack pointer
;;R0給MSP寄存器
MSR MSP, R0

;;Check if boot space corresponds to test memory

LDR R0,=0x00000004
LDR R1, [R0]
;;R1=0x08000004 OR R1=0x20000004 OR R1=0x1FXX XXXX
;;when R1=R1=0x1FXX XXXX,we can know that Reset_Handler'sAddress is not right,
;;it maybe in reserved or systemmemory or optionbyte,we must remap address for start
;;Logical shift right by register LSRS

LSRS R1, R1, #24
;R2=0x0000001F
LDR R2,=0x1F
CMP R1, R2

BNE ApplicationStart

;; SYSCFG clock enable
;RCC_APB2ENR,0x40021018
LDR R0,=0x40021018
LDR R1,=0x00000001
STR R1, [R0]

;; Set CFGR1 register with flash memory remap at address 0
;SYS_CFGR1,0x40010000
LDR R0,=0x40010000
LDR R1,=0x00000000
STR R1, [R0]
ApplicationStart
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP

; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
;;B . 無限循環(huán)
B .
ENDP
HardFault_Handler
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP

Default_Handler PROC

EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_CRS_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT CEC_CAN_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]


WWDG_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
TSC_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
CEC_CAN_IRQHandler
USB_IRQHandler

B .

ENDP

ALIGN

;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB

EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit

ELSE

IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap

__user_initial_stackheap

LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR

ALIGN

ENDIF

END

;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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